Design of Novel CMOS DCCII with Reduced Parasitics and its All-Pass Filter Applications - (:unkn) unknown (KAUNAS UNIV TECHNOLOGY, 2016)
In this paper, a novel translinear loop based, high performance Complementary Metal-Oxide-Semiconductor (CMOS) second-generation differential current conveyor (DCCII) is introduced. By using super source follower transistors, very low equivalent impedances are obtained at input terminals x(n) and x(p). In addition, new voltage-mode (VM) and current-mode (CM) first-order all-pass filters (APFs) are proposed to highlight the performance of the designed CMOS DCCII. The designed CMOS implementation is simulated with HSpice using AMS 0.35 mu m real process parameters. It consumes only 1.3 mW power with using +/- 1.25 V power supply voltages. The simulation results of the proposed CMOS DCII circuit and the experimental results for designed VM APF are in very good agreement with the theoretical ones.
Keywords: Analog signal processing; all-pass filter; current-mode; voltage-mode; DCCII; reduced parasitic; super source follower; translinear loop; DIFFERENCING BUFFERED AMPLIFIER; INDUCTANCE CIRCUITS