Person: TOPCUOĞLU, HALUK RAHMİ
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TOPCUOĞLU
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HALUK RAHMİ
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Publication Metadata only Scheduling opportunities for asymmetrically reliable caches(ACADEMIC PRESS INC ELSEVIER SCIENCE, 2019) TOPCUOĞLU, HALUK RAHMİ; Arslan, Sanem; Topcuoglu, Haluk Rahmi; Kandemir, Mahmut Taylan; Tosun, OguzModern systems become more vulnerable to soft errors with technology scaling. Providing fault tolerance strategies on all structures in a system may lead to high energy consumption. Our framework with asymmetrically reliable caches with at least one protected core and several unprotected cores dynamically assigns the software threads executing critical code fragments to the protected core(s) with the FCFS-based algorithm. The framework can provide good reliability, performance, and power consumption trade-offs compared with the fully protected and unprotected systems. However, FCFS-based scheduling algorithm may degrade the system performance and unfairly slow down applications for some workloads. In this paper, a set of scheduling algorithms is proposed to improve both the system performance and fairness perspectives. Various static priority techniques that require preliminary information about the applications (such as their execution order, cache usage, number of requests sent to the protected core(s), and total burst time spent on the protected core(s)) are implemented and evaluated. On the other hand, dynamic priority techniques that target to equalize the total time spent of applications on the protected core(s) or the progress of the applications' requests are presented. Extensive evaluations using multi application workloads validate significant improvements of our static and dynamic priority scheduling techniques on system performance and fairness over the FCFS algorithm. (C) 2019 Elsevier Inc. All rights reserved.Publication Metadata only Protecting code regions on asymmetrically reliable caches(Springer Verlag, 2016) TOPCUOĞLU, HALUK RAHMİ; Arslan S., Topcuoglu H.R., Kandemir M.T., Tosun O.Cache structures in a multicore system are considerably susceptible to soft errors. Protecting all caches using fault tolerance techniques has notable overheads on performance and power consumption. In this paper, we propose an enhanced protection mechanism for reliabilitybased critical code regions of the applications on asymmetrically reliable cores which have different error-tolerant cache structures. In this system, software threads which execute reliability-based critical code regions are mapped onto the protected cores, whereas the threads which execute noncritical regions are mapped to the unprotected ones, dynamically during the execution. Our experimental evaluations indicate that the proposed system improves Silent Data Corruption (SDC) rate by 66% with 22% performance loss and 1.2% more power consumption for selected applications relative to the unprotected caches on average. © Springer International Publishing Switzerland 2016.Publication Metadata only A selective protection scheme of applications using asymmetrically reliable caches(ELSEVIER, 2017) TOPCUOĞLU, HALUK RAHMİ; Arslan, Sanem; Topcuoglu, Haluk Rahmi; Kandemir, Mahmut Taylan; Tosun, OguzCache structures in a multicore system are highly vulnerable to soft errors. Enabling fault tolerance capabilities on all cache structures in a system is inefficient in terms of performance and power consumption. In this study, we propose an enhanced protection mechanism for code segments, which are critical in terms of reliability, by utilizing asymmetrically reliable cores under performance and power constraints. Our proposed system contains at least one high-reliability core, which has an ECC-protected L1 cache, and several low-reliability cores, which have no protection mechanisms. Reliability-based critical code regions are assumed to be high-priority functions, which are extracted by examining the execution time percentages and the program's call graph in our framework, statically. Software threads that invoke one of the high-priority functions are bound to the high-reliability cores dynamically during the execution, while the threads that execute the remaining functions are bound to the low-reliability cores. As part of the experimental analysis, our proposed framework is compared with traditional fully protected and unprotected configurations with respect to performance, power and reliability metrics for various applications of the benchmarks. Our framework exploits the benefits of providing the reliability-based critical regions of the applications exclusively by offering notable power and cost savings with close performance and reliability values for the set of functions reported in the experimental results. (C) 2016 Elsevier B.V. All rights reserved.Publication Metadata only Asymmetrically reliable caches for multicore architectures under performance and energy constraints(SPRINGER, 2016) TOPCUOĞLU, HALUK RAHMİ; Arslan, Sanem; Topcuoglu, Haluk Rahmi; Kandemir, Mahmut Taylan; Tosun, OguzCache structures in a multicore system are more vulnerable to soft errors due to high transistor density. Protecting all caches unselectively has notable overhead on performance and energy consumption. In this study, we propose asymmetrically reliable caches to supply reliability need of the system using sufficient additional hardware under the performance and energy constraints. In our framework, a chip multiprocessor is composed of a high reliability core which has ECC protection, and a set of low reliability cores which have no protection on their data caches. Between two types of cores, there is also a middle-level reliability core which has only parity check. Application threads are mapped on the different cores in terms of reliability based on their critical data usage. The experimental results for selected applications show that our proposed techniques improve reliability with considerable performance and energy overhead on the average compared to traditional unsafe caches.