Implementation and applications of a ternary threshold logic gate

Abstract

Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a digital circuit designer. Most of the times, the designer sacrifices power consumption and chip area to decrease delay for a given technology node. To overcome this problem, we propose the ternary threshold logic gate. We have implemented the proposed gate by combining the threshold logic with the ternary logic. Then, we have constructed basic building blocks of a ternary ALU (as ternary logic gates, comparator, and arithmetic circuits) using the proposed ternary threshold logic gate. We have compared these building blocks and implemented with the proposed gate, with the ones implemented using different technologies. Via simulations, we have shown that the proposed gate may be utilized to decrease delay, power consumption, and chip area of ternary circuits. Thus, the proposed ternary threshold logic gate can be used to decrease delay, power consumption, and chip area of ternary circuits.