Publication:
Reliability-aware core partitioning in chip multiprocessors

Simple item page
dc.contributor.authorTOPCUOĞLU, HALUK RAHMİ
dc.contributor.authorsOz, Isil; Topcuoglu, Haluk Rahmi; Kandemir, Mahmut; Tosun, Oguz
dc.date.accessioned2022-03-12T18:07:12Z
dc.date.available2022-03-12T18:07:12Z
dc.date.issued2012
dc.description.abstractExecuting multiple applications concurrently is an important way of utilizing the computational power provided by emerging chip multiprocessor (CMP) architectures. However, this multiprogramming brings a resource management and partitioning problem, for which one can find numerous examples in the literature. Most of the resource partitioning schemes proposed to date focus on performance or energy centric strategies. In contrast, this paper explores reliability-aware core partitioning strategies targeting CMPs. One of our schemes considers both performance and reliability objectives by maximizing a novel combined metric called the vulnerability-delay product (VDP). The vulnerability component in this metric is represented with Thread Vulnerability Factor (TVF), a recently proposed metric for quantifying thread vulnerability for multicores. Execution time of the given application represents the delay component of the VDP metric. As part of our experimental analysis, proposed core partitioning schemes are compared with respect to normalized weighted speedup, normalized weighted reliability loss and normalized weighted vulnerability delay product gain metrics for various workloads of benchmark applications. (C) 2012 Elsevier B.V. All rights reserved.
dc.identifier.doi10.1016/j.sysarc.2012.02.005
dc.identifier.eissn1873-6165
dc.identifier.issn1383-7621
dc.identifier.urihttps://hdl.handle.net/11424/230994
dc.identifier.wosWOS:000304287100005
dc.language.isoeng
dc.publisherELSEVIER
dc.relation.ispartofJOURNAL OF SYSTEMS ARCHITECTURE
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.subjectReliability
dc.subjectThread vulnerability
dc.subjectMulticores
dc.subjectCore partitioning
dc.subjectReliability-aware computing
dc.titleReliability-aware core partitioning in chip multiprocessors
dc.typearticle
dspace.entity.typePublication
local.avesis.idf302d5a8-7624-40fa-8fd8-ddd229b80dc0
local.import.packageSS17
local.indexed.atWOS
local.indexed.atSCOPUS
local.journal.numberofpages17
oaire.citation.endPage176
oaire.citation.issue3-4
oaire.citation.startPage160
oaire.citation.titleJOURNAL OF SYSTEMS ARCHITECTURE
oaire.citation.volume58
relation.isAuthorOfPublication54c6a927-2146-44b3-90ee-33dac6503317
relation.isAuthorOfPublication.latestForDiscovery54c6a927-2146-44b3-90ee-33dac6503317

Files

Collections

Research Outputs